Still as busy as a working bee. Towards the end of last week a critical bug that caused simulation hang was filed on me. As we are taping out soon, the only way to fix this is netlist ECO, and hence the nightmare. For 2 nights in a row I was staying up late until 12am in the company, and was dead tired. I wonder how i pull all nighters every so often back in college? Getting old already must be.

Netlist ECO is no fun. It hurts my eye by tracing bunch of logic gates and wire that don't correlate too well with RTL. The best way to do this is writing down every single term, and de-morgan it. Fellow engineers, when was the last time you actually use de morgan's law? And with this sweet little girl, I finally hacked through the gates successfully:)

Now, Fixing bug is one thing, explaining to upper management the reason of this bug slipping through verification is another thing. No doubt it's my mistake, but i hate it when they put all the blame on us designer for not verifying all the corner cases. We are only human. When will they learn to do things the right way by hiring more verification engineers?